This paper provides an overview of the development process of advanced Quicksim (and QuickPath) timing models that are used in a full custom IC library. These timing models provide propagation delays based on their connected load and routing. The data used for these propagation delays is automatically obtained from an Accusim script.

Dave Kenney is an independent consultant specializing in Mentor Graphics libraries and applications. Dave consulted at Sarnoff for 2 1/2 years in the areas of IC and PCB design. President of EDA Consulting, Inc. http://davekenney.com

The David Sarnoff Research Center, a subsidiary of SRI International, is a renowned leader in electronic imaging. http://www.sarnoff.com

The design of this library allows the IC process (transistor size, silicon properties, etc.) to be defined in easily to modify global parameters. After modification, Accusim scripts can immediately update all the timing models in the library. Thus the library can be quickly transitioned to a new IC process and or existing designs can be transitioned and simulated with a new IC process.

In version 8, Quicksim supports advanced timing models that Mentor refers to as Technology Files. These Tech files allow the definition of pin to pin propagation delays using equations that can include functions for factoring in the load properties of their diven gates and routing. Additionally the Tech files provide other functions for constraint warnings such as minimum pulse width, setup and hold, etc.

Tech files are created from Ascii code and are compiled using the Mentor "tc" compiler. The compiler requires a component argument that is used to register the component interface with the resulting binary.

An IC library was built consisting of digital components (flip flops, inverters, nand, nor, etc.) with each component consisting of:

1. Graphical symbol
2. Digital functional model
3. Accusim schematic model
4. Tech file timing model

The digital models defined the Quicksim functionality and included Builtin, Quickpart Table model, and Quickpart Compiled schematics. The Accusim model was a transistor level schematic sheet capable of Accusim/Spice analysis. And the Tech file consisted of Ascii statements that defined a delay function for each input to output path.

The delays were modeled using linear equations that are quite accurate for cmos gates. Thus as shown in the figure below, a zero load resulted in an intrinsic delay of D0, a load of one gate resulted in (D0 + Slope*L1), two gates resulted in (D0 + Slope*L2) and so on. Mathematically: Delay = K1 + K2*Load delay

Knowing this linear relationship of the load and delay allows K1 and K2 to be derived by just measuring (using Accusim) the noLoad and 1xLoad delays.

The first step would be to determine all the input to output paths. And then determining the rise and/or fall stimulus necessary to exercise each path. This was as simple as reviewing the underlying Accusim schematic.

Each delay path definition would specify a transition (rise or fall) on an input pin to a transition on an output pin. The definition would also specify the delay value using the linear equation (Delay = K1 + K2*Load).

The K1 and K2 values would be assigned variable names that are later defined by statements inserted automatically by an Accusim script that measures the delays. The load is defined using functions that can obtain properties from the net attached to the output pin (on the schematic where the symbol is instanciated).

The Tech file functions used to determine the load are SIM_$SUM_EVAL() and SIM_$NET_EVAL(). The SIM_$SUM_EVAL() function has the ability to scan the connected net and return the sum of pin properties from the gates being diven (specifically CAP_PIN). The SIM_$NET_EVAL() function is used to obtain the value of the net property CAP_NET.

The CAP_PIN property would be attached to every input pin and has a value representing the capacitive load. CAP_PIN is derived from the transistors connected to the input pin of the underlying Accusim schematic.

The CAP_NET property is a net property representing the capacitive load from the routing. CAP_NET is added by the ICextract tool that analyzes the layout route. Prior to layout, CAP_NET has a default value that uses a function capable of returning an estimated value based on the number of pins being driven.

The specific details of the delay equations along with examples are described in the Technology File Development Manual (Bold Browser).

A test schematic is created to measure the no-load and 1x-load delays used to compute the K1 and K2 coefficients. The schematic would contain two instances of the component. One instance would represent the no-load, the second instance would represent the 1x-load (by having a gate connected to its output pin).

Accusim could then be used to measure the delays. This required first defining the initial setup and force stimulus for each delay measurement. Then running the simulation and executing a measurement function between the input and output pins.

Since the Accusim results need to be inserted into the Tech file, an Ample script would be written that performs the complete task. A script for each component would be written and for each delay path perform:

1. Setup initial conditions
2. Apply force stimulus
3. Measure no-load and 1x-load delay
4. Compute K1 and K2 and insert values in Tech file.

There was also a function written that computed CAP_PIN based on the spice parameters of the underlying transistors connected to each input pin. This value would also be automatically inserted into the Tech file. Note, the Tech file can add properties to a pin.

To completely automate the update task, the above commands would be placed in an Accusim "here" script that would also reexecute the Tech file compiler.

These models were used to fully simulate a 625K transistor IC. Quicksim allowed the design to be first simulated quickly with timing disabled, then simulated with full timing. The design was simulated at various levels in the hierarchy and then fully simulated at the top level. The top level simulation also included the back annotation of the routing.

There were several timing problems detected and corrected using Quicksim and QuickPath. The IC was delivered on schedule with first pass success.

The library, the design, or parts of the design can now be reused with another sub-micron technology by changing the global parameters and reexecuting the Accusim scripts.

• John Armer was a co-developer (DSRC)
• Bruce Ahrens provided methodology and consulting (MGC)
• The System and Integrated Circuit team lead by Bill Mayweather (DSRC)